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Complete, Quad, 14/16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC
iCMOSTM
FEATURES
Preliminary Technical Data
AD5744/AD5764
GENERAL DESCRIPTION
The AD5744/64 is a quad, 14/16-bit serial input, voltage output digital-to analog converter that operates from supply voltages of 12 V up to 15 V. Nominal full-scale output range is 10 V, provided are integrated output amplifiers, reference buffers, internal reference, and proprietary power-up/power-down control circuitry. It also features a digital I/O port that may be programmed via the serial interface, and an analog temperature sensor. The part incorporates digital offset and gain adjust registers per channel. The AD5744/64 is a high performance converter that offers guaranteed monotonicity, integral nonlinearity (INL) of 1 LSB, low noise and 10 s settling time and includes an on-chip 5 V reference with a reference tempco of 10 ppm/C max. During power-up (when the supply voltages are changing), Vout is clamped to 0V via a low impedance path. The AD5744/64 uses a serial interface that operates at clock rates of up to 30 MHz and is compatible with DSP and microcontroller interface standards. Double buffering allows the simultaneous updating of all DACs. The input coding is programmable to either twos complement or Offset binary formats. The asynchronous clear function clears all DAC registers to either bipolar zero or zero-scale depending on the coding used. The AD5744/64 is ideal for both closed-loop servo control and open-loop control applications. The AD5744/64 is available in a 32-lead TQFP package, and offers guaranteed specifications over the -40C to +85C industrial temperature range. See functional block diagram, Figure 1.
Complete quad 14/16-bit D/A converter Programmable output range: 10 V, 10.25 V, or 10.5 V 1 LSB max INL error, 1 LSB max DNL error Low noise : 60 nV/Hz Settling time: 10s max Integrated reference buffers Internal reference, 10 ppm/C On-chip temp sensor, 5C accuracy Output control during power-up/brownout Programmable short-circuit protection Simultaneous updating via LDAC Asynchronous CLR to zero code Digital offset and gain adjust Logic output control pins DSP/microcontroller compatible serial interface Temperature range:-40C to +85C iCMOSTM Process Technology
APPLICATIONS
Industrial automation Open/Closed-loop servo control Process control Data acquisition systems Automatic Test Equipment Automotive test and measurement High accuracy instrumentation
iCMOSTM Process Technology For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher-voltage levels, iCMOS is a technology platform that enables the development of analog ICs capable of 30V and operating at +/-15V supplies while allowing dramatic reductions in power consumption and package size, and increased AC and DC performance. Rev. PrA
15-Nov-04 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
AD5744/AD5764
TABLE OF CONTENTS
Functional Block Diagram .............................................................. 3 Specifications..................................................................................... 4 AC Performance Characteristics ................................................ 6 Timing Characteristics ................................................................ 7 Absolute Maximum Ratings.......................................................... 10 ESD Caution................................................................................ 10 Pin Configuration and Function Descriptions........................... 11 Terminology .................................................................................... 13 typical performance characteristics ............................................. 15 General Description ....................................................................... 16 dac architecture........................................................................... 16 Reference Buffers........................................................................ 16 Serial interface ............................................................................ 16 Simultaneous Updating Via LDAC .......................................... 17 transfer function ......................................................................... 18 Asynchronous Clear (CLR)....................................................... 18 Function Register ....................................................................... 19 DAta register ............................................................................... 20
Preliminary Technical Data
Coarse gain register.................................................................... 20 Fine gain register ........................................................................ 21 offset register............................................................................... 21 AD5744/64 Features....................................................................... 22 Analog Output Control ............................................................. 22 Digital Offset and Gain Control............................................... 22 Programmable Short-Circuit protection................................. 22 Digital I/O Port........................................................................... 22 Temperature Sensor ................................................................... 22 Local ground offset adjust......................................................... 22 applications information ............................................................... 23 typical operating circuit............................................................. 23 layout guidelines......................................................................... 24 Isolated interface ........................................................................ 24 microprocessor interfacing ....................................................... 24 Evaluation board ........................................................................ 26 Outline Dimensions ....................................................................... 27 Ordering Guide .......................................................................... 27
REVISION HISTORY
Revision PrA 15-Nov-04: Preliminary Version
Rev. PrA 15-Nov-04| Page 2 of 27
Preliminary Technical Data FUNCTIONAL BLOCK DIAGRAM
PGND AVDD AVSS AVDD AVSS REFOUT REFGND VREF AB VOLTAGE MONITOR AND CONTROL
AD5744/AD5764
RSTOUT
RSTIN
DVCC DGND +5V REFERENCE REFERENCE BUFFERS
ISCC
14/16 SDIN SCLK SYNC SDO INPUT SHIFT REGISTER AND CONTROL LOGIC
INPUT REG A GAIN REG A OFFSET REG A
DAC 14/16 REG A
G1 DAC A G2 AGNDA VOUTA
INPUT REG B GAIN REG B OFFSET REG B D0 D1 INPUT REG C GAIN REG C OFFSET REG C BIN/2SCOMP INPUT REG D
DAC 14/16 REG B
G1 DAC B G2 AGNDB VOUTB
DAC 14/16 REG C
G1 DAC C G2 AGNDC G1 DAC D G2 VOUTD VOUTC
DAC 14/16 REG D
CLR
GAIN REG D OFFSET REG D REFERENCE BUFFERS TEMP SENSOR
AGNDD
LDAC
VREF CD
TEMP
Figure 1. Functional Block Diagram
Rev. PrA 15-Nov-04| Page 3 of 27
AD5744/AD5764
SPECIFICATIONS
Preliminary Technical Data
AVDD = +11.4 V to +16.5 V, AVSS = -11.4 V to -16.5 V, AGND = DGND = REFGND = PGND=0 V; REFAB = REFCD= 5 V Ext; DVCC = 2.7 V to 5.5 V, RLOAD = 10 k, CL = 200 pF. All specifications TMIN to TMAX, unless otherwise noted. Table 1.
Parameter ACCURACY Resolution Relative Accuracy (INL) Differential Nonlinearity Bipolar Zero Error A Grade1 16 14 4 1 1 B Grade1 16 14 2 1 1 C Grade1 16 14 1 1 1 Unit Bits LSB max LSB max mV max Test Conditions/Comments AD5764 AD5744 Guaranteed monotonic At 25C. Error at other temperatures obtained using bipolar zero TC. At 25C. Error at other temperatures obtained using zero code TC. At 25C. Error at other temperatures obtained using gain TC.
Bipolar Zero TC Zero Code Error
2 1
2 1
2 1
ppm FSR/C max mV max
Zero Code TC Gain Error
2 0.02
2 0.02
2 0.02
ppm FSR/C max % FSR max
Gain TC DC Crosstalk2 REFERENCE INPUT/OUTPUT Reference Input2 Reference Input Voltage DC Input Impedance Input Current Reference Range Reference Output Output Voltage Reference TC Output Noise(0.1 Hz to 10 Hz) Noise Spectral Density OUTPUT CHARACTERISTICS2 Output Voltage Range3 Output Voltage TC Output Voltage Drift VS Time Short Circuit Current Load Current Capacitive Load Stability RL = RL = 10 k DC Output Impedance DIGITAL INPUTS2 VIH, Input High Voltage
2 0.5
2 0.5
2 0.5
ppm FSR/C max LSB max
5 1 10 1/5 4.999/5.001 10 TBD TBD 10 13 2 TBD 10 1 200 TBD 0.3
5 1 10 1/5 4.999/5.001 10 TBD TBD 10 13 2 TBD 10 1 200 TBD 0.3
5 1 10 1/5 4.999/5.001 10 TBD TBD 10 13 2 TBD 10 1 200 TBD 0.3
V nom M min A max V min/max V min/max ppm/C max V p-p typ nV/Hz typ V min/max V min/max ppm FSR/C max ppm FSR/1000 Hours typ mA max mA max pF max pF max max
1% for specified performance Typically 100 M Typically 30 nA
At 25C
AVDD/AVSS = 11.4 V AVDD/AVSS = 16.5 V
RISCC = 6 K , See Figure ??? For specified performance
DVCC = 2.7 V to 5.5 V, JEDEC compliant 2 2 2 V min
1 2
Temperature range -40C to +85C; typical at +25C. Device functionality is guaranteed to +105C with degraded performance. Guaranteed by characterization. Not production tested. 3 Output amplifier headroom requirement is 1.4 V min.
Rev. PrA 15-Nov-04| Page 4 of 27
Preliminary Technical Data
Parameter VIL, Input Low Voltage Input Current Pin Capacitance DIGITAL OUTPUTS (D0,D1, SDO) 2 Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage High Impedance Leakage Current High Impedance Output Capacitance TEMP SENSOR Accuracy Output Voltage @ 25C Output Voltage Scale Factor Output Voltage Range Output Load Current Power On Time POWER REQUIREMENTS AVDD/AVSS DVCC Power Supply Sensitivity4 VOUT/VDD AIDD AISS DICC Power Dissipation A Grade1 0.8 10 10 0.4 DVCC - 1 0.4 DVCC - 0.5 1 5 B Grade1 0.8 10 10 0.4 DVCC - 1 0.4 DVCC - 0.5 1 5 C Grade1 0.8 10 10 0.4 DVCC - 1 0.4 DVCC - 0.5 1 5 Unit V max A max pF max V max V min V max V min A max pF typ
AD5744/AD5764
Test Conditions/Comments Total for All Pins. TA = TMIN to TMAX.
DVCC= 5 V 10%, sinking 200 A DVCC = 5 V 10%, Sourcing 200 A DVCC = 2.7 V to 3.6 V, Sinking 200 A DVCC = 2.7 V to 3.6 V, Sourcing 200 A SDO only SDO only
1 5 1.5 5 0/3.0 200 10 11.4/16.5 2.7/5.5 -85 3.75 2.75 1 244
1 5 1.5 5 0/3.0 200 10 11.4/16.5 2.7/5.5 -85 3.75 2.75 1 244
1 5 1.5 5 0/3.0 200 10 11.4/16.5 2.7/5.5 -85 3.75 2.75 1 244
C typ C max V typ mV/C typ V min/max A max ms typ V min/max V min/max dB typ mA/Channel max mA/Channel max mA max mW typ
At 25C -40C < T <+85C
Current source only. To within 5C
Outputs unloaded Outputs unloaded VIH = DVCC, VIL = DGND. TBD mA typ 12 V operation output unloaded
4
Guaranteed by characterization. Not production tested. Rev. PrA 15-Nov-04| Page 5 of 27
AD5744/AD5764
AC PERFORMANCE CHARACTERISTICS
Preliminary Technical Data
AVDD = +11.4 V to +16.5 V, AVSS = -11.4 V to -16.5 V, AGND = DGND = REFGND = PGND=0 V; REFAB = REFCD= 5 V Ext; DVCC = 2.7 V to 5.5 V, RLOAD = 10 k, CL = 200 pF. All specifications TMIN to TMAX, unless otherwise noted. Guaranteed by design and characterization, not production tested. Table 2.
Parameter DYNAMIC PERFORMANCE Output Voltage Settling Time A Grade 8 10 1 5 5 5 100 5 B Grade 8 10 1 5 5 5 100 5 5 1 0.1 45 1 60 80 C Grade 8 10 1 5 5 5 100 5 5 1 0.1 45 1 60 80 Unit s typ s max s max V/s typ nV-s typ mV max dB typ nV-s typ nV-s typ nV-s typ LSB p-p typ V rms max kHz typ nV/Hz typ nV/Hz typ Test Conditions/Comments Full-scale step 512 LSB step settling @ 16 Bits
Slew Rate Digital-to-Analog Glitch Energy Glitch Impulse Peak Amplitude Channel-to-Channel Isolation DAC-to-DAC Crosstalk Digital Crosstalk Digital Feedthrough Output Noise (0.1 Hz to 10 Hz) Output Noise (0.1 kHz to 100 kHz)5 1/f Corner Frequency Output Noise Spectral Density Complete System Output Noise Spectral Density6
Effect of input bus activity on DAC output under test
Measured at 10 kHz Measured at 10 kHz
5 6
Guaranteed by design and characterization. Not production tested. Includes noise contributions from integrated reference buffers, 14/16-bit DAC and output amplifier.
Rev. PrA 15-Nov-04| Page 6 of 27
Preliminary Technical Data
TIMING CHARACTERISTICS
AD5744/AD5764
AVDD = +11.4 V to +16.5 V, AVSS = -11.4 V to -16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFAB = REFCD= 5 V Ext; DVCC = 2.7 V to 5.5 V, RLOAD = 10 k, CL = 200 pF. All specifications TMIN to TMAX, unless otherwise noted. Table 3.
Parameter7,8,9 t1 t2 t3 t4 t5 10 t6 t7 t8 t9 t10 t11 t12 t13 t14 t1511,12 t1612 t1712 Limit at TMIN, TMAX 33 13 13 13 13 40 5 0 20 20 5 10 20 12 20 8 20 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min s max ns min s max ns max ns min ns min Description SCLK cycle time SCLK high time SCLK low time SYNC falling edge to SCLK falling edge setup time 24th SCLK falling edge to SYNC rising edge Minimum SYNC high time Data setup time Data hold time SYNC rising edge to LDAC falling edge LDAC pulse width low LDAC falling edge to DAC output response time DAC output settling time CLR pulse width low CLR pulse activation time SCLK rising edge to SDO valid SCLK falling edge to SYNC rising edge SYNC rising edge to LDAC falling edge
7 8 9
Guaranteed by design and characterization. Not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. See Figure 2, Figure 3, and Figure 4. 10 Stand-alone mode only. 11 Measured with the load circuit of Figure 5. 12 Daisy-chain mode only.
Rev. PrA 15-Nov-04| Page 7 of 27
AD5744/AD5764
t1
SCLK 1 2 24
Preliminary Technical Data
t6
t4
SYNC
t3
t2
t5
t7
SDIN DB23
t8
DB0
t9
LDAC
t10
t12
t11
VOUT
LDAC = 0
t12
t11
VOUT
CLR
t13
t14
VOUT
04641-PrA-002
Figure 2. Serial Interface Timing Diagram
t1
SCLK 24 48
t6 t4
SYNC
t3
t2
t5 t16
t8 t7
SDIN DB23 DB0 DB23 DB0
INPUT WORD FOR DAC N
t15
DB23
INPUT WORD FOR DAC N+1 DB0
SDO
UNDEFINED LDAC
INPUT WORD FOR DAC N
t17
Figure 3. Daisy Chain Timing Diagram
Rev. PrA 15-Nov-04| Page 8 of 27
04641-PrA-003
t10
Preliminary Technical Data
AD5744/AD5764
24 48
SCLK
SYNC
SDIN
DB23
DB0
DB23
DB0
INPUT WORD SPECIFIES REGISTER TO BE READ SDO DB23
NOP CONDITION
UNDEFINED
SELECTED REGISTER DATA CLOCKED OUT
Figure 4. Readback Timing Diagram
200A
IOL
TO OUTPUT PIN
200A
IOH
Figure 5. Load Circuit for SDO Timing Diagram
Rev. PrA 15-Nov-04| Page 9 of 27
04641-PrA-004
CL 50pF
VOH (MIN) OR VOL (MAX)
04641-PrA-005
DB0
AD5744/AD5764
ABSOLUTE MAXIMUM RATINGS
TA = 25C unless otherwise noted. Transient currents of up to 100 mA will not cause SCR latch-up. Table 4.
Parameter AVDD to AGND, DGND AVSS to AGND, DGND DVCC to DGND Digital Inputs to DGND Digital Outputs to DGND REF IN to AGND, PWRGND REF OUT to AGND VOUTA,B,C,D to AGND AGND to DGND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature (TJ max) 32-Lead TQFP Package, JA Thermal Impedance Reflow Soldering Peak Temperature Time at Peak Temperature Rating -0.3 V to +17 V +0.3 V to -17 V -0.3 V to +7 V -0.3 V to DVCC + 0.3 V -0.3 V to DVCC + 0.3 V -0.3 V to +17 V AVSS to AVDD AVSS to AVDD -0.3 V to +0.3 V -40C to +85C -65C to +150C 150C TBDC/W
Preliminary Technical Data
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
220C 10 sec to 40 sec
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrA 15-Nov-04| Page 10 of 27
Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BIN/2sCOMP AVDD AVSS TEMP REFGND REFOUT REFCD REFAB
AD5744/AD5764
32
25 24 PIN 1 INDICATOR
SYNC SCLK SDIN SDO CLR LDAC D0 D1
1
AD5744/64
TOP VIEW (Not to Scale)
AGNDA VOUTA VOUTB AGNDB AGNDC VOUTC VOUTD AGNDD
17 16
8 9
Figure 6. 32-Lead TQFP Pin Configuration Diagram
Table 5. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 Mnemonic SYNC SCLK13 SDIN13 SDO CLR13 LDAC Function Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred in on the falling edge of SCLK. Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds up to 30 MHz. Serial Data Input. Data must be valid on the falling edge of SCLK. Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode. Active Low Input. Asserting this pin sets the DAC registers to 0x0000. Load DAC. Logic input. This is used to update the DAC registers and consequently the analog output. When tied permanently low, the addressed DAC register is updated on the 24th clock of the serial register write. If LDAC is held high during the write cycle, the DAC input register is updated but the output is held off until the falling edge of LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC. D0 and D1 form a digital I/O port. The user can configure these pins as inputs or outputs that are configurable and readable over the serial interface. When configured as inputs, these pins have weak internal pull-ups to DVCC. Reset Logic Output. This is the output from the on-chip voltage monitor used in the reset circuit. If desired, it may be used to control other system components. Reset Logic Input. This input allows external access to the internal reset logic. Applying a Logic 0 to this input resets the DAC output to 0 V. In normal operation, RSTIN should be tied to Logic 1. Digital GND Pin. Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V. When programmed as outputs, D0 and D1 are referenced to DVCC. Positive Analog Supply Pins. Voltage ranges from 11.4 V to 16.5 V. Ground Reference Point for Analog Circuitry. Negative Analog Supply Pins. Voltage ranges from -11.4 V to -16.5 V.
7, 8
D0, D1
9 10
RSTOUT RSTIN
11 12 13, 31 14 15, 30
DGND DVCC AVDD PGND AVSS
13
Internal pull-up device on this logic input. Therefore, it can be left floating and will default to a logic high condition.
Rev. PrA 15-Nov-04| Page 11 of 27
RSTOUT RSTIN DGND DVCC AVDD PGND AVSS ISCC
Preliminary Technical Data
Pin No. 16 17 18 Mnemonic ISCC AGNDD VOUTD Function This pin us used in association with an external resistor to AGND to program the short-circuit current of the output amplifiers. Ground Reference Pin for DAC D Output amplifier. Analog Output Voltage of DAC D. Buffered output with a nominal full-scale output range of 10 V. The output amplifier is capable of directly driving a 10 k, 200 pF load. Analog Output Voltage of DAC C. Buffered output with a nominal full-scale output range of 10 V. The output amplifier is capable of directly driving a 10 k, 200 pF load. Ground Reference Pin for DAC C Output Amplifier. Ground Reference pin for DAC B Output Amplifier. Analog Output Voltage of DAC B. Buffered output with a nominal full-scale output range of 10 V. The output amplifier is capable of directly driving a 10 k, 200 pF load. Analog Output Voltage of DAC A. Buffered output with a nominal full-scale output range of 10 V. The output amplifier is capable of directly driving a 10 k, 200 pF load. Ground Reference Pin for DAC A Output Amplifier. External Reference Voltage Input for Channels A and B. Reference input range is 1 V to 5 V; programs the full-scale output voltage. REFIN = 5 V for specified performance. External Reference Voltage Input for Channels C and D. Reference input range is 1 V to 5 V; programs the full-scale output voltage. REFIN = 5 V for specified performance. Reference Output. This is the buffered reference output from the internal voltage reference. The internal reference is 5 V 1 mV, with a reference tempco of 10 ppm/C. Reference Ground Return for the Reference Generator and Buffers. This pin provides an output voltage proportional to temperature. The output voltage is 1.5 V typical at 25C; variation with temperature is 5 mV/C. Determines the DAC Coding. When set to a logic high, input coding is offset binary. When set to a logic low, input coding is twos complement. (See Table 6 and Table 7)
19
VOUTC
20 21 22
AGNDC AGNDB VOUTB
23
VOUTA
24 25 26 27
AGNDA REFAB REFCD REFOUT
28 29 32
REFGND TEMP BIN/2sCOMP
Rev. PrA 15-Nov-04| Page 12 of 27
Preliminary Technical Data TERMINOLOGY
90% of the output signal and is given in V/s. Relative Accuracy For the DAC, relative accuracy or Integral Nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure ?. Differential Nonlinearity Differential Nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figures ?. Monotonicity A DAC is monotonic, if the output either increases or remains constant for increasing digital input code. The AD5744/64 is monotonic over its full operating temperature range Bipolar Zero Error Bipolar zero error is the deviation of the analog output from the ideal half-scale output of 0 V when the DAC register is loaded with 0x8000 (Offset Binary coding) or 0x0000 (2sComplement coding) Full-Scale Error Full-scale error is a measure of the output error when full-scale code is loaded to the DAC register. Ideally the output voltage should be full scale value - 1 LSB. Full-scale error is expressed in percentage of full-scale range. A plot of full-scale error vs. temperature can be seen in Figure ?. Negative Full-Scale Error / Zero Scale Error Negative full-scale error is the error in the DAC output voltage when 0x0000 (Offset Binary coding) or 0x8000 (2sComplement coding) is loaded to the DAC register. Ideally the output voltage should be negative full scale value - 1 LSB. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output to settle to a specified level for a full-scale input change. Slew Rate The slew rate of a device is a limatation in the rate of change of the output voltage. The output slewing speed of a voltageoutput D/A converter is usually limited by the slew rate of the amplifier used at its output. Slew rate is measured from 10% to DC Crosstalk This is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC while monitoring another DAC. It is expressed in V. DAC-to-DAC Crosstalk This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV secs and is measured when the digital input code is changed by 1 LSB at the major carry transition (7FFF Hex to 8000 Hex). See Figure ?. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated. It is specified in nV secs and measured with a full-scale code change on the data bus, i.e., from all 0s to all 1s and vice versa. Power Supply Sensitivity Power supply sensitivity indicates how the output of the DAC is affected by changes in the power supply voltage. Gain Error This is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal, expressed as a percentage of the full-scale range. Total Unadjusted Error Total Unadjusted Error (TUE) is a measure of the output error taking all the various errors into account. A typical TUE vs. code plot can be seen in Figure ?. Zero-Code Error Drift This is a measure of the change in zero-code error with a change in temperature. It is expressed in V/C. Gain Error Drift This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/C.
Rev. PrA 15-Nov-04| Page 13 of 27
Preliminary Technical Data
another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-s. Channel-to-Channel Isolation This is the ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference input of another DAC. It is measured in dB.
Rev. PrA 15-Nov-04| Page 14 of 27
Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS
Rev. PrA 15-Nov-04| Page 15 of 27
Preliminary Technical Data GENERAL DESCRIPTION
The AD5744/64 is a quad 14/16-bit, serial input, bipolar voltage output DAC. It operates from supply voltages of 11.4 V to 16.5 V and has a buffered output voltage of up to 10.5 V. Data is written to the AD5744/64 in a 24-bit word format, via a 3-wire serial interface. The device also offers an SDO pin, which is available for daisy chaining or readback. The AD5744/64 incorporates a power-on reset circuit, which ensures that the DAC registers power up loaded with 0x0000. The AD5744/64 also features a digital I/O port that may be programmed via the serial interface, an analog temperature sensor, on-chip 10 ppm/C voltage reference, on-chip reference buffers and per channel digital gain and offset registers.
SERIAL INTERFACE
The AD5744/64 is controlled over a versatile 3-wire serial interface that operates at clock rates of up to 30 MHz and is compatible with SPI, QSPI, MICROWIRE and DSP standards.
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input, SCLK. The input register consists of a read/write bit, three register select bits, three DAC address bits and 14/16 data bits as shown in Table 8.The timing diagram for this operation is shown in Figure 2. Upon power-up the DAC registers are loaded with zero code (0x0000). The corresponding output voltage depends on the state of the BIN/2sCOMP pin. If the BIN/2sCOMP pin is tied to DGND then the data coding is 2sComplement and the outputs will power-up to 0V. If the BIN/2sCOMP pin is tied high then the data coding is Offset binary and the outputs will power-up to Negative Full-scale.
DAC ARCHITECTURE
The DAC architecture of the AD5744/64 consists of a 14/16-bit current-mode segmented R-2R DAC. The simplified circuit diagram for the DAC section is shown in Figure 13. The four MSBs of the 14/16-bit data word are decoded to drive 15 switches, E1 to E15. Each of these switches connects one of the 15 matched resistors to either AGND or IOUT. The remaining 12 bits of the data word drive switches S0 to S11 of the 12-bit R-2R ladder network.
Vref 2R 2R R R R
Standalone Operation
The serial interface works with both a continuous and noncontinuous serial clock. A continuous SCLK source can only be used if SYNC is held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used and SYNC must be taken high after the final clock to latch the data. The first falling edge of SYNC starts the write cycle. Exactly 24 falling clock edges must be applied to SCLK before SYNC is brought back high again; if SYNC is brought high before the 24th falling SCLK edge, the write is aborted. If more than 24 falling SCLK edges are applied before SYNC is brought high, the input data will be corrupted. The input register addressed is updated on the rising edge of SYNC. In order for another serial transfer to take place, SYNC must be brought low again. After the end of the serial data transfer, data is automatically transferred from the input shift register to the input register of the addressed DAC. When the data has been transferred into the input register of the addressed DAC, all DAC registers and outputs can be updated by taking LDAC low while SYNC is high.
2R
2R
2R
2R
2R
R/8 E15 E14 E1 S11 S10 S0
AGND 4 MSBs DECODED INTO 15 EQUAL SEGMENTS 12 BIT R-2R LADDER
VOUT
Figure 7. DAC Ladder Structure
REFERENCE BUFFERS
The AD5744/64 can operate with either an external or internal reference. The reference inputs (REFAB and REFCD) have an input range up to 5 V. This input voltage is then used to provide a buffered positive and negative reference for the DAC cores. The positive reference is given by + VREF = 2* VREF While the negative reference to the DAC cores is given by -VREF = -2*VREF These positive and negative reference voltages (along with the gain register values) define the output ranges of the DACs.
Rev. PrA 15-Nov-04| Page 16 of 27
Preliminary Technical Data
68HC11* MOSI SCK PC7 PC6 MISO AD5744/64* SDIN SCLK SYNC LDAC SDO
containing the exact number of clock cycles must be used and SYNC must be taken high after the final clock to latch the data.
Readback Operation
Readback mode is invoked by setting the R/W bit = 1 in the serial input register write. With R/W = 1, Bits A2-A0, in association with Bits REG2 , REG1, and REG0, select the register to be read. The remaining data bits in the write sequence are don't cares. During the next SPI write, the data appearing on the SDO output will contain the data from the previously addressed register. For a read of a single register, the NOP command can be used in clocking out the data from the selected register on SDO. The readback diagram in Figure 4 shows the readback sequence. For example, to read back the fine gain register of Channel A on the AD5744/64, the following sequence should be implemented. First, write 0xA0XXXX to the AD5744/64 input register. This configures the AD5744/64 for read mode with the fine gain register of Channel A selected. Note that all the data bits, DB15 to DB0, are don't cares. Follow this with a second write, a NOP condition, 0x00XXXX. During this write, the data from the fine gain register is clocked out on the SDO line, i.e., data clocked out will contain the data from the fine gain register in Bits DB5 to DB0.
SDIN AD5744/64* SCLK SYNC LDAC SDO R SDIN AD5744/64* SCLK SYNC LDAC SDO
SIMULTANEOUS UPDATING VIA LDAC
After data has been transferred into the input register of the DACs, there are two ways in which the DAC registers and DAC outputs can be updated. Depending on the status of both SYNC and LDAC.
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 8. Daisy chaining the AD5744/64
Individual DAC Updating Daisy-Chain Operation
For systems that contain several devices, the SDO pin may be used to daisy-chain several devices together. This daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. The first falling edge of SYNC starts the write cycle. The SCLK is continuously applied to the input shift register when SYNC is low. If more than 24 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is clocked out on the rising edge of SCLK and is valid on the falling edge. By connecting the SDO of the first device to the DIN input of the next device in the chain, a multidevice interface is constructed. Each device in the system requires 24 clock pulses. Therefore, the total number of clock cycles must equal 24N, where N is the total number of AD5744/64s in the chain. When the serial transfer to all devices is complete, SYNC is taken high. This latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register. The serial clock may be a continuous or a gated clock. A continuous SCLK source can only be used if SYNC is held low for the correct number of clock cycles. In gated clock mode, a burst clock In this mode, LDAC is held low while data is being clocked into the input shift register. The addressed DAC output is updated on the rising edge of SYNC.
Simultaneous Updating of All DACs
In this mode, LDAC is held high while data is being clocked into the input shift register. All DAC outputs are updated by taking LDAC low any time after SYNC has been taken high. The update now occurs on the falling edge of LDAC.
Rev. PrA 15-Nov-04| Page 17 of 27
Preliminary Technical Data
OUTPUT I/V AMPLIFIER VREFIN 16-BIT DAC VOUT
Table 7. Ideal output voltage to input Code relationship for the AD5744
Digital Input Offset Binary Data Coding MSB 11 10 10 01 00 1111 0000 0000 1111 0000 1111 0000 0000 1111 0000 LSB 1111 0001 0000 1111 0000 VOUT
+2 VREF x (8192/8192) +2 VREF x (1/8192) 0V -2 VREF x (1/8192) -2 VREF x (8192/8192) VOUT +2 VREF x (8192/8192) +2 VREF x (1/8192) 0V -2 VREF x (1/8192) -2 VREF x (8192/8192)
Analog Output
LDAC
DAC REGISTER
INPUT REGISTER
SCLK SYNC SDIN
INTERFACE LOGIC
SDO
Figure 9. Simplified Serial Interface showing input loading circuitry for one DAC Channel
TRANSFER FUNCTION
Table 6 and Table 7 Show the ideal input code to output voltage relationship for the AD5744/64 for both Offset binary and twos complement data coding. Table 6. Ideal output voltage to input code relationship for the AD5764
Digital Input Offset Binary Data Coding MSB 1111 1000 1000 0111 0000 MSB 0111 0000 0000 1111 1000 1111 0000 0000 1111 0000 1111 0000 0000 1111 0000 LSB 1111 0001 0000 1111 0000 LSB 1111 0001 0000 1111 0000 VOUT
+2 VREF x (32767/32768) +2 VREF x (1/32768) 0V -2 VREF x (1/32768) -2 VREF x (32767/32768) VOUT +2 VREF x (32767/32768) +2 VREF x (1/32768) 0V -2 VREF x (1/32768) -2 VREF x (32767/32768)
Twos Complement Data Coding MSB LSB 01 1111 1111 1111 00 0000 0000 0001 00 0000 0000 0000 11 1111 1111 1111 10 0000 0000 0000
The output voltage expression for the AD5764 is given by:
Analog Output
D VOUT = -2 x VREFIN + 4 x VREFIN 65536
The output voltage expression for the AD5744 is given by:
D VOUT = -2 x VREFIN + 4 x VREFIN 16384
where: D is the decimal equivalent of the code loaded to the DAC. VREFIN is the reference voltage applied at the REFIN pin.
Twos Complement Data Coding 1111 0000 0000 1111 0000 1111 0000 0000 1111 0000
ASYNCHRONOUS CLEAR (CLR)
CLR is an active low, level sensitive clear that allows the outputs to be cleared to either 0 V (Offset binary coding) or negative full scale (twos complement coding). It is necessary to maintain CLR low for a minimum amount of time (refer to Figure 3) for the operation to complete. When the CLR signal is returned high, the output remains at the cleared value until a new value is programmed. The CLR signal has priority over LDAC and SYNC. A clear can also be initiated through software by writing the command 0x04XXXX to the AD5744/64.
Rev. PrA 15-Nov-04| Page 18 of 27
Preliminary Technical Data
Table 8. AD5744/64 Input Register Format
MSB DB23 R/W DB22 0 DB21 REG2 DB20 REG1 DB19 REG0 DB18 A2 DB17 A1 DB16 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DATA DB7 DB6 DB5 DB4 DB3 DB2 DB1 LSB DB0
Table 9. Input Register Bit Functions
R/W REG2, REG1, REG0 Indicates a read from or a write to the addressed register. Used in association with the address bits to determine if a read or write operation is to the data register, offset register, gain register, or function register. REG2 REG1 REG0 Function 0 0 0 Function Register 0 1 0 Data Register 0 1 1 Coarse Gain Register 1 0 0 Fine Gain Register 1 0 1 Offset Register These bits are used to decode the DAC channels A2 A1 A0 Channel Address 0 0 0 DAC A 0 0 1 DAC B 0 1 0 DAC C 0 1 1 DAC D 1 0 0 ALL DACs Data Bits
A2, A1, A0
D15 - D0
FUNCTION REGISTER
The Function Register is addressed by setting the three REG bits to 000. The values written to the address bits and the data bits determine the function addressed. The Functions available through the function register are shown in Table 10 and
Table 11. Table 10. Function Register Options
REG2 0 0 REG1 0 0 REG0 0 0 A2 0 0 A1 0 0 A0 0 1 DB15 .. DB6 Don't Care DB5 LocalGroundOffset Adjust DB4 DB3 DB2 NOP, Data = Don't Care D1 Value D0 D1 Direction Direction CLR, Data = Don't Care LOAD, Data = Don't Care DB1 D0 Value DB0 SDO Disable
0 0
0 0
0 0
1 1
0 0
0 1
Rev. PrA 15-Nov-04| Page 19 of 27
Preliminary Technical Data
Table 11. Explanation of Function Register Options
NOP Local-GroundOffset Adjust D0 / D1 Direction D0 / D1 Value No operation instruction used in readback operations. Set by the user to enable local-ground-offset adjust function. Cleared by the user to disable local-ground-offset adjust function (default). Set by the user to enable D0/D1 as outputs. Cleared by the user to enable D0/D1 as inputs (default). Have weak internal pull-ups. I/O port status bits. Logic values written to these locations determine the logic outputs on the D0 and D1 pins when configured as outputs. These bits indicate the status of the D0 and D1 pins when the I/O port is active as an input. When enabled as inputs, these bits are don't cares during a write operation. Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default). Addressing this function resets the DAC outputs to 0 V in twos complement mode and negative full scale in binary mode. Addressing this function updates the DAC registers and consequently the analog outputs.
SDO Disable CLR LOAD
DATA REGISTER
The Data register is addressed by setting the three REG bits to 010. The DAC address bits select with which DAC Channel the Data transfer is to take place (Refer to Table 9). The data bits are in positions D15 to D0 for the AD5764 as shown in Table 12 and D13 to D0 for the AD5744 as shown in Table 13. Table 12. Programming the AD5764 Data Register
REG2 0 REG1 1 REG0 0 A2 A1 A0 DAC Address DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 16 Bit DAC Data DB6 DB5 DB4 DB3 DB2 DB1 DB0
Table 13. Programming the AD5744 Data Register
REG2 0 REG1 1 REG0 0 A2 A1 A0 DAC Address DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 14 Bit DAC Data DB7 DB6 DB5 DB4 DB3 DB2 DB1 X DB0 X
COARSE GAIN REGISTER
The Coarse Gain Register is addressed by setting the three REG bits to 011. The DAC address bits select with which DAC Channel the Data transfer is to take place (Refer to Table 9). The Coarse Gain Register is a 2-bit register and allows the user to select the output range of each DAC as shown in Table 15. Table 14. Programming the Coarse Gain Register
REG2 0 REG1 1 REG0 1 A2 A1 A0 DAC Address DB15 .... DB2 Don't Care DB1 CG1 DB0 CG0
Table 15. Output Range Selection
Output Range 10 V 10.25 V 10.5 V CG1 0 0 1 CG0 0 1 0
Rev. PrA 15-Nov-04| Page 20 of 27
Preliminary Technical Data
FINE GAIN REGISTER
The Fine Gain Register is addressed by setting the three REG bits to 100. The DAC address bits select with which DAC Channel the Data transfer is to take place (Refer to Table 9). The Fine Gain Register is a 6-bit register and allows the user to adjust the gain of each DAC channel by -32 LSBs to +31 LSBs in 1 LSB steps as shown in Table 16 and Table 17.
Table 16. Programming AD5764 Fine Gain Register
REG2 1 REG1 0 REG0 0 A2 A1 DAC Address A0 DB15 .... DB6 Don't Care DB5 FG5 DB4 FG4 DB3 FG3 DB2 FG2 DB1 FG1 DB0 FG0
Table 17. Fine Gain Register Options
Gain Adjustment +31 LSBs +30 LSBs No Adjustment -31 LSBs -32 LSBs FG5 0 0 0 1 1 FG4 1 1 0 0 0 FG3 1 1 0 0 0 FG2 1 1 0 0 0 FG1 1 1 0 0 0 FG0 1 0 0 1 0
OFFSET REGISTER
The Offset Register is addressed by setting the three REG bits to 101. The DAC address bits select with which DAC Channel the Data transfer is to take place (Refer to Table 9). The Offset Register is an 8-bit register and allows the user to adjust the offset of each channel by - 15.875 LSBs to + 16 LSBs in steps of 1/8 LSB as shown in Table 18 and Table 19. Table 18. Programming the Offset Register
REG2 1 REG1 0 REG0 1 A2 A1 A0 DAC Address DB15 .... DB8 Don't Care DB7 OF7 DB6 OF6 DB5 OF5 DB4 OF4 DB3 OF3 DB2 OF2 DB1 OF1 DB0 OF0
Table 19. Offset Register options
Offset Adjustment +15.875 LSBs +16.5 LSBs No Adjustment -15.875 LSBs -16 LSBs OF7 0 0 0 1 1 OF6 1 1 0 0 0 OF5 1 1 0 0 0 OF4 1 1 0 0 0 OF3 1 1 0 0 0 OF2 1 1 0 0 0 OF1 1 1 0 0 0 OF0 1 0 0 1 0
Rev. PrA 15-Nov-04| Page 21 of 27
Preliminary Technical Data AD5744/64 FEATURES
ANALOG OUTPUT CONTROL
In many industrial process control applications, it is vital that the output voltage be controlled during power up and during brownout conditions. When the supply voltages are changing, the VOUT pin is clamped to 0 V via a low impedance path. To prevent the output amp being shorted to 0 V during this time, transmission gate G1 is also opened. These conditions are maintained until the power supplies stabilize and a valid word is written to the DAC register. At this time, G2 opens and G1 closes. Both transmission gates are also externally controllable via the Reset In (RSTIN) control input. For instance, if RSTIN is driven from a battery supervisor chip, the RSTIN input is driven low to open G1 and close G2 on power-off or during a brownout. Conversely, the on-chip voltage detector output (RSTOUT) is also available to the user to control other parts of the system. The basic transmission gate functionality is shown in Figure 10. The resistor value is calculated as follows;
R=
60 Isc
If the ISCC pin is left unconnected the short circuit current limit defaults to 5 mA. It should be noted that limiting the short circuit current to a small value can affect the slew rate of the output when driving into a capacitive load, therefore the value of short-circuit current programmed should take into account the size of the capacitive load being driven.
DIGITAL I/O PORT
The AD5744/64 contains a 2-bit digital I/O port (D1 and D0); these bits can be configured as inputs or outputs independently, and can be driven or have their values read back via the serial interface. The I/O port signals are referenced to DVCC and DGND. When configured as outputs, they can be used as control signals to multiplexers or can be used to control calibration circuitry elsewhere in the system. When configured as inputs, the logic signals from limit switches, for example can be applied to D0 and D1 and can be read back via the digital interface.
RSTOUT VOLTAGE MONITOR AND CONTROL G1
RSTIN
TEMPERATURE SENSOR
The on-chip temperature sensor provides a voltage output that is linearly proportional to the Centigrade temperature scale. The typical accuracy of the temperature sensor is 1C at +25C and 5C over the -40C to +105C range. Its nominal output voltage is 1.5V at +25C, varying at 5 mV/C, giving a typical output range of 1.175V to 1.9 V over the full temperature range. Its low output impedance, low self heating, and linear output simplify interfacing to temperature control circuitry and A/D converters.
G2 AGNDA
Figure 10. Analog Output Control Circuitry
DIGITAL OFFSET AND GAIN CONTROL
The AD5744/64 incorporates a digital offset adjust function with a 16 LSB adjust range and 0.125 LSB resolution. The gain register allows the user to adjust the AD5744/64's full-scale output range. The full-scale output can be programmed to achieve full-scale ranges of 10 V, 10.25 V, and 10.5 V. A fine gain trim is also available, allowing a trim range of 16 LSB in 1 LSB steps.
04641-PrA-008
VOUTA
LOCAL GROUND OFFSET ADJUST
The AD5744/64 incorporates a Local Ground Offset Adjust feature which when enabled in the Function Register adjusts the DAC outputs for voltage differences between The individual DAC ground pins and the REFGND pin ensuring that the DAC output voltages are always with respect to the local DAC ground pin. For instance if pin AGNDA is at +5mV with respect to the REFGND pin and VOUTA is measured with respect to AGNDA then a +5mV error will result, enabling the Local Ground Offset Adjust feature will offset VOUTA by +5mV eliminating the error.
PROGRAMMABLE SHORT-CIRCUIT PROTECTION
The short-circuit current of the output amplifiers can be programmed by inserting an external resistor between the ISCC pin and AGND. The programmable range for the current is 500 A to 10 mA, corresponding to a resistor range of 120 k to 6 k.
Rev. PrA 15-Nov-04| Page 22 of 27
Preliminary Technical Data APPLICATIONS INFORMATION
TYPICAL OPERATING CIRCUIT
Figure 11 shows the typical operating circuit for the AD5744/64. The only external components needed for this precision 14/16-bit DAC are decoupling capacitors on the supply pins, R-C connection from REFOUT to REFAB and REFCD and a short circuit current setting resistor. Because the device incorporates a voltage reference, and reference buffers, it eliminates the need for an external bipolar reference and associated buffers. This leads to an overall saving in both cost and board space. In the circuit below, VDD and VSS are both connected to 15 V, but VDD and VSS can operate with supplies from 11.4 V to 16.5 V. In Figure 11, AGNDA is connected to REFGND, but the option of Force/Sense is included on this device, if required by the user.
+15V -15V
in the voltage reference is reflected in the outputs of the device. There are four possible sources of error to consider when choosing a voltage reference for high accuracy applications: initial accuracy, temperature coefficient of the output voltage, long term drift and output voltage noise. Initial accuracy error on the output voltage of an external reference could lead to a full-scale error in the DAC. Therefore, to minimize these errors, a reference with low initial accuracy error specification is preferred. Also, choosing a reference with an output trim adjustment, such as the ADR425, allows a system designer to trim system errors out by setting the reference voltage to a voltage other than the nominal. The trim adjustment can also be used at temperature to trim out any error. Long term drift is a measure of how much the reference output voltage drifts over time. A reference with a tight lon-term drift specification ensures that the overall solution remains relatively stable over its entire lifetime. The temperature coefficient of a reference's output voltage affects INL, DNL and TUE. A reference with a tight tempaerature coefficient specifiaction should be chosen to reduce the dependence of the DAC output voltage on ambient conditions.
10 F 100 nF
10 F 100 nF
TEMP BIN/2SCOMP
32 31 30 29 28 27 26 25
AVDD
REFOUT
REFCD
REFAB
TEMP
SYNC SCLK SDIN SDO LDAC D0 D1
1 2 3 4 5 6 7 8
SYNC SCLK SDIN SDO CLR LDAC D0 D1
BIN/2SCOMP
REFGND
AVSS
+5V
3k
10 F
AGNDA 24 VOUTA 23 VOUTB 22 VOUTA VOUTB
AD5744/64
AGNDB 21 AGNDC 20 VOUTC 19 VOUTD 18 AGNDD 17 VOUTC VOUTD
RSTOUT
RSTIN
DGND
PGND
DVCC
AVDD
AVSS
9
10 11 12 13 14 15 16
100 nF 100 nF
6k
RSTOUT RSTIN
ISCC
In high accuracy applications, which have a relatively low noise budget, reference output voltage noise needs to be considered. Choosing a reference waith as low an output noise voltage as practical for the system resolution required is important. Precision voltage references such as the ADR435 (XFET design) produce low output noise in the 0.1 Hx to 10 Hz region. However, as the circuit bandwidth increases, filtering the output of the reference may be required to minimise the output noise.
10 F
100 nF
Table 20. Partial List of Precision References Recommended for use with the AD5744/64
Initial Accuracy (mV max) 6 6 5 6 2.5 Long-Term Drift (ppm typ) 30 50 50 50 15 Temp Drift (ppm/ C max) 3 3 3 25 10 0.1 Hz to 10 Hz Noise (V p-p typ) 3.4 3.4 15 5 4
10 F
10 F
+5V +15V -15V
Figure 11. Typical operating circuit
Precision Voltage Reference Selection
To achieve the optimum performance from the AD5744/64 over it's full operating temperature range an external voltage reference must be used. Thought should be given to the selection of a precision voltage reference. The AD5744/64 has two reference inputs, REFAB and REFCD. The voltages applied to the reference inputs are used tomprovide a buffered positiver and negative reference for the DAC cores. Therefore, any error
Part No. ADR435 ADR425 ADR02 ADR395 AD586
Rev. PrA 15-Nov-04| Page 23 of 27
Preliminary Technical Data
LAYOUT GUIDELINES
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5744/64 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5744/64 is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. The AD5744/64 should have ample supply bypassing of 10 F in parallel with 0.1 F on each supply located as close to the package as possible, ideally right up against the device. The 10 F capacitors are the tantalum bead type. The 0.1 F capacitor should have low effective series resistance (ESR) and low effective series inductance (ESI) such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. The power supply lines of the AD5744/64 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. A ground line routed between the SDIN and SCLK lines helps reduce crosstalk between them (not required on a multilayer board, which has a separate ground plane, but separating the lines helps). It is essential to minimize noise on the reference inputs, because it couples through to the DAC output. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feed through the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane, while signal traces are placed on the solder side. DAC is not required, the LDAC pin may be tied permanently low. The DAC can then be updated on the rising edge of SYNC.
DVCC
CONTROLLER CONTROL OUT TO LDAC
SYNC OUT
TO SYNC
SERIAL CLOCK OUT
TO SCLK
SERIAL DATA OUT
TO SDIN
OPTO-COUPLER
Figure 12. Isolated Interface
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5744/64 is via a serial bus that uses standard protocol compatible with microcontrollers and DSP processors. The communications channel is a 3-wire (minimum) interface consisting of a clock signal, a data signal, and a synchronization signal. The AD5744/64 requires a 24-bit data word with data valid on the falling edge of SCLK. For all the interfaces, the DAC output update may be done automatically when all the data is clocked in, or it may be done under the control of LDAC. The contents of the DAC register may be read using the readback function.
AD5744/64 to MC68HC11 Interface
Figure 13 shows an example of a serial interface between the AD5744/64 and the MC68HC11 microcontroller. The serial peripheral interface (SPI) on the MC68HC11 is configured for master mode (MSTR = 1), clock polarity bit (CPOL = 0), and the clock phase bit (CPHA = 1). The SPI is configured by writing to the SPI control register (SPCR)---- see the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK of the AD5744/64, the MOSI output drives the serial data line (DIN) of the AD5744/64, and the MISO input is driven from SDO. The SYNC is driven from one of the port lines, in this case PC7. When data is being transmitted to the AD5744/64, the SYNC line
ISOLATED INTERFACE
In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled. Opto-isolators can provide voltage isolation in excess of 3 kV. The serial loading structure of the AD5744/64 makes it ideal for opto-isolated interfaces, because the number of interface lines is kept to a minimum. Figure 12 shows a 4channel isolated interface to the AD5744/64. To reduce the number of opto-isolators, if the simultaneous updating of the
Rev. PrA 15-Nov-04| Page 24 of 27
Preliminary Technical Data
(PC7) is taken low and data is transmitted MSB first. Data appearing on the MOSI output is valid on the falling edge of SCK. Eight falling clock edges occur in the transmit cycle, so, in order to load the required 24-bit word, PC7 is not brought high until the third 8-bit word has been transferred to the DAC's input shift register. through the SPORT control register and should be configured as follows: internal clock operation, active low framing, and 24-bit word length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. As the data is clocked out of the DSP on the rising edge of SCLK, no glue logic is required to interface the DSP to the DAC. In the interface shown, the DAC output is updated using the LDAC pin via the DSP. Alternatively, the LDAC input could be tied permanently low, and then the update takes place automatically when TFS is taken high.
ADSP2101/ ADSP2103*
DR
MC68HC11*
MISO MOSI SCLK PC7
AD5744/64*
SDO SDIN SCLK SYNC
AD5744/64*
SDO SDIN SCLK SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY
DT SCLK TFS
Figure 13. AD5744/64 to MC68HC11 Interface LDAC is controlled by the PC6 port output. The DAC can be updated after each 3-byte transfer by bringing LDAC low. This example does not show other serial lines for the DAC. If CLR were used, it could be controlled by port output PC5, for example.
RFS FO LDAC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 14. AD5744/64 to ADSP2101/ADSP2103 Interface
AD5744/64 to 8051 Interface
The AD5744/64 requires a clock synchronized to the serial data. For this reason, the 8051 must be operated in Mode 0. In this mode, serial data enters and exits through RxD, and a shift clock is output on TxD. P3.3 and P3.4 are bit programmable pins on the serial port and are used to drive SYNC and LDAC, respectively. The 8051 provides the LSB of its SBUF register as the first bit in the data stream. The user must ensure that the data in the SBUF register is arranged correctly, because the DAC expects MSB first. When data is to be transmitted to the DAC, P3.3 is taken low. Data on RxD is clocked out of the microcontroller on the rising edge of TxD and is valid on the falling edge. As a result, no glue logic is required between this DAC and the microcontroller interface. The 8051 transmits data in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Because the DAC expects a 24-bit word, SYNC (P3.3) must be left low after the first eight bits are transferred. After the third byte has been transferred, the P3.3 line is taken high. The DAC may be updated using LDAC via P3.4 of the 8051.
AD5744/64 to PIC16C6x/7x Interface
The PIC16C6x/7x synchronous serial port (SSP) is configured as an SPI master with the clock polarity bit set to 0. This is done by writing to the synchronous serial port control register (SSPCON). See the PIC16/17 Microcontroller User Manual. In this example, I/O port RA1 is being used to pulse SYNC and enable the serial port of the AD5744/64. This microcontroller transfers only eight bits of data during each serial transfer operation; therefore, three consecutive write operations are needed. Figure 15 shows the connection diagram.
PIC16C6x/7x*
SDI/RC4 SDO/RC5 SCLK/RC3 RA1
AD5744/64*
SDO SDIN SCLK SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY
AD5744/64 to ADSP2101/ADSP2103 Interface
An interface between the AD5744/64 and the ADSP2101/ ADSP2103 is shown in Figure 14. The ADSP2101/ADSP2103 should be set up to operate in the SPORT transmit alternate framing mode. The ADSP2101/ADSP2103 are programmed
Figure 15. AD5744/64 to PIC16C6x/7x Interface
Rev. PrA 15-Nov-04| Page 25 of 27
Preliminary Technical Data
EVALUATION BOARD
The AD5744/64 comes with a full evaluation board to aid designers in evaluating the high performance of the part with a minimum of effort. All that is required with the evaluation board is a power supply, and a PC. The AD5744/64 evaluation kit includes a populated, tested AD5744/64 printed circuit board. The evaluation board interfaces to the USB interface of the PC. Software is available with the evaluation board, which allows the user to easily program the AD5744/64. The software runs on any PC that has Microsoft Windows(R) 98/2000/NT/XP installed. An application note is available that gives full details on operating the evaluation board.
Rev. PrA 15-Nov-04| Page 26 of 27
Preliminary Technical Data OUTLINE DIMENSIONS
1.20 MAX 0.75 0.60 0.45
24 25
9.00 SQ
17 16
TOP VIEW
(PINS DOWN)
7.00 SQ
32 1 8
9
0.15 0.05
0.80 BSC 1.05 1.00 0.95 SEATING PLANE
0.45 0.37 0.30 7 0
COMPLIANT TO JEDEC STANDARDS MS-026ABA
Figure 16. 32-Lead Thin Quad Flatpack [TQFP] (SU-32) Dimensions shown in millimeters
ORDERING GUIDE
Model AD5764CSU AD5764BSU AD5764ASU AD5744CSU AD5744BSU AD5744ASU Function Quad 16-Bit DAC Quad 16-Bit DAC Quad 16-Bit DAC Quad 14-Bit DAC Quad 14-Bit DAC Quad 14-Bit DAC INL 1 LSB Max 2 LSB Max 4 LSB Max 1 LSB Max 2 LSB Max 4 LSB Max Package Description 32-Lead TQFP 32-Lead TQFP 32-Lead TQFP 32-Lead TQFP 32-Lead TQFP 32-Lead TQFP Package Option SU-32 SU-32 SU-32 SU-32 SU-32 SU-32
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
PR05303-0-11/04(PrA)
Rev. PrA 15-Nov-04| Page 27 of 27
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